The Core Memory Project



NCR Criterion Series

NCR Criterion V-8555m

The NCR V-8555M is a medium-scale, general-purpose computer system that exploits the latest state-of-the-art technologies to set a new standard for data processing productivity. NCR Criterion V-8555mV-8500 system architecture employs multi-position, plug-in modules for ease of expansion and configuration flexibility. Extensive use of microcircuitry and advanced packaging technology means more power in less physical space.

A complete complement of mainframe features, peripherals and terminals, and comprehensive software allow total flexibility in hardware and operating environment selection. V-8500 system design is based on a concept of modular, distributed intelligence that allows overall workload to be divided among internal modules, each with its own set of tasks. Features such as start-of-day confidence level checking, automatic internal memory error detection and correction, and specialized diagnostics mean greater reliability, serviceability, and productivity.

Flexible Multiprocessing

The NCR V-8555M uses the powerful Virtual Resource Executive (VRX) operating system. This proven operating system features full dynamic resource allocation, virtual memory with no rigid memory partitioning, and other features that provide ease of use and improved productivity.

VRX-MP is an extension of this system which provides multiprocessing capabilities. Up to three additional processors can be tightly-coupled and share all system resources. VRX-MP provides the ability to link different members of the V-8500 family in a single multiprocessing complex.

NCR V-8555M hardware architecture employs the same modular approach that has consistently proved its viability since inception of the first 8500 family systems. Independent subsystems are grouped through modular architecture into an integrated base system. This modular architecture allows expansion of the base readily and economically by incorporating additional subsystems.

These subsystems can include up to three additional processors joined in a tightly-coupled multiprocessing environment that appears to be a uniprocessor system to operators, programmers, and application software. Multiprocessing systems extend the base architecture by incorporating high-speed Interbus Communication Adapters (ICA) to provide higher performance levels and greater reliability through inherent redundancies.

This flexibility has made it possible to:

Implement new hardware components, affording greater speed and efficiency.
Provide extensive back-up capabilities for maximum system availability and maintainability.
Build in extensive, economical growth potential.
 Ensure the ability to incorporate new technologies and procedures as they emerge, to provide still higher levels of performance and reliability throughout the life of the system.


The Internal Transfer Subsystem, which comprises a high-speed (56MB bandwidth), 4-byte wide internal transfer bus and its interfaces, handles all communications among the other subsystems. The bus is central to V-8500M architecture and allows subsystems to function concurrent with and independent of each other for maximum processing efficiency. It also permits the addition of new subsystems easily and economically.

Internal communications are prioritized so that the highest priority subsystem has use of the bus when two or more subsystems request it at the same time. No subsystem, however, can use more than one- half of the total cycles available, which means that a single, high- priority subsystem can never monopolize the bus for an extended period.


The Memory Subsystem consists of four modules and the interface, timing, and control logic that allows it to function independent of other subsystems. High-speed RAM chips provide a read memory access time of 370 ns and a write memory access time of 440 ns.

Error Detection and Correction

NCR V-8555M systems provide automatic single-bit memory error correction and double-bit memory error detection for high reliability.

Memory Sizes

Base V-8555M memory is 0.5 megabyte expandable in 0.5 megabyte increments to a maximum of 2 megabytes. (1 megabyte = 1,048,576 bytes.)


Software and application object code instructions are interpreted and executed by the Processor Subsystem under the direction of micro- programmed firmware. Firmware serves as the interface between software and each subsystem to ensure that hardware facilities are used in the most effective and efficient way to accomplish results required by system design. All V-8555M processor firmware resides in a high-speed (84 ns cycle time) instruction storage unit specifically tailored to meet higher performance requirements.


Pipelining is a technique of instruction overlapping that allows execution of one microcode instruction per processor cycle (84 ns) once the pipeline has been loaded. Instructions are divided into logical segments or stages of performance. The number of stages depends upon whether or not the instruction involves a memory access. Multiple stages can then be processed simultaneously to achieve one execution during every cycle.


The Service Subsystem provides the interface between the Internal Transfer Subsystem and various devices for operator/system communications (keyboards, displays, console printers, system card reader, and flexible disk drive). It services these devices on an ‘interrupt” basis: a signal from any device, including the Internal Transfer Subsystem, causes the Service Subsystem to execute the firmware service routine for that device. The firmware routine then determines the cause of the interruption and performs the required service without having to interrupt the Processor Subsystem.


Input/Output Subsystem components and characteristics are determined by the types of peripherals attached to the system, but can include any or all of the following:

Input/Output Link Controllers

I/O Link Controllers - interface with peripherals through I/O Link Adapters, which are either built into individual peripherals or handle strings of peripherals, depending upon the nature of the device. Each I/O Link Controller supports up to four Link Adapters; the number of controllers per system will vary from none to a maximum of six, depending upon individual configuration requirements and I/O options selected.

Common Trunk Controller

Interfaces for standard NCR common trunks can also be included in the system to permit migration of certain existing peripherals that are not adaptable to I/O Link architecture. A maximum of two low-speed (75KB transfer rate) trunks and one medium-speed (225KB) trunk may be attached to any system, together with any number of high-speed (1.2MB) trunks, so long as the total number of IOLC’s and common trunks does not exceed six.

Integrated Disk Controller

The system will also accommodate one or two Integrated Disk Controllers in addition to the maximum number of I/O Link Controllers and common trunks permitted. Each controller drives up to three strings of disk spindles and provides direct memory access, so that processing units do not have to be interrupted during data transfer. Two controllers operating on a system can transfer data simultaneously for two separate spindles residing on different strings.


An extensive complement of terminals and peripherals allows maximum flexibility to meet individual user configuration requirements. Terminals include general-purpose units, such as CRT displays and remote printers, and specialized terminals with varying degrees of intelligence for financial, retail, medical, educational, government, and commercial/industrial applications.

Paper Media File Peripherals

Include card readers, card punches, punched tape readers, and MICA sorters.

Printers provide a wide variety of printed output on single-, multi-part, and preprinted continuous forms at up to 2,000 lines per minute.

Magnetic Tape Handlers are available in PE, NAZI, and GCR modes, with recording densities up to 6,250 bits per inch and transfer rates up to 1.2 megabytes.

Disk Units include both removable and fixed disks with up to 1,092MB capacity per unit and 1.2 megabyte transfer rates.


Processor Cycle Time                               84 ns
Main Memory (Base)                                   0.5MB
Read Access Time                                     440 ns
Write Access Time                                    370 ns
Memory Increments                                  0.5MB
Maximum Main Memory                              2MB
Integrated Disk Controllers (Maximum)    2
— Strings/IDC (max.)                                 3
— Spindles/String (max.)                           8
Integrated Communications (Maximum)  20 lines


The Core Memory Project. Started 04.02.2005.
Copyright © Aleksandrs Guba. All Rights Reserved