The Core Memory Project



NCR Criterion Series

NCR Criterion V-8450

The NCR V-8450, designed for a wide range of processing environments, is a general-purpose computer system that covers a wide spectrum of information processing for NCR Criterion V-8450the small-to medium-scale installation. It offers more memory and data storage capacity, processing features, and peripherals than most comparable systems. And, it incorporates state-of-the-art technologies in computer design and implementation.

Emitter-coupled logic circuitry for greater reliability and speed.
MOS memories with single-bit error correction and double-bit error detection.
Direct memory access for high- speed peripherals.
Internal transfer bus architecture for faster throughput.
Pipeline processing with a 112 ns cycle time.
Comprehensive software to simplify overall operations aids in debugging and fine-tuning system for maximum performance.
High-level telecommunications software with greater flexibility and programming ease for system analysts and application programmers.
Sophisticated diagnostics both at the local and remote levels to ensure maximum performance and reliability for the systems.

The NCR V-8450 adds a new dimension to virtual storage computer systems. It is supported by sophisticated peripherals and terminals, high-level software, telecommunications, and worldwide service for all phases of implementation and operation. And, it offers the cost-conscious organization a complete system with a greater price/performance ratio for the information processing investment.

System Hardware

The NCR V-8450 system architecture is completely modular, incorporating standard internal subsystems into an integrated base. Modular construction provides the basis for distributed intelligence design in which multiple subsystems can function concurrently and independently for maximum throughput.

A basic system comprises a central processor with its processing and internal transfer subsystems, an integrated memory subsystem, and an input/output control subsystem. The basic system can be readily and economically expanded by adding memory, I/O subsystems, an optional integrated disk subsystem, and an optional integrated
communication subsystem.

Virtual machine architecture offers important price/performance benefits.

Combines more power in less physical space through advanced engineering techniques and extensive use of microcircuitry.
Distributes the processing workload among several independent subsystems to maintain a smooth flow of data through the system.
Employs multi-position, plug-in modules for ease of expansion and configuration flexibility.


The NCR V-8450 system architecture consolidates microprogrammable subsystems.

Hardware subsystems include the internal transfer subsystem, the integrated memory subsystem, and I/O subsystem. These subsystems have all functions built into the hardware and perform these functions in response to signals or messages from other subsystems or peripherals.

Microprogrammable subsystems include the processor, integrated disk, and integrated communication subsystems. These subsystems execute micro commands that are linked together by microprograms in order to generate individual functions. Micro commands perform a single basic task that is executed in one machine cycle.
Subsystems are directed by firmware and testware loaded into control store memory from flexible disk. This approach makes possible multiple virtual machine operation and simplifies system modification and the addition of hardware subsystems.


The Processor Subsystem interprets and executes software and application program object instructions and controls operation of the total system. Object instructions are fetched from main memory and distributed to specific registers within the processor. The instruction's operation code is interpreted, and control is passed to appropriate routines for executing the function. If data in main memory is changed as a result of execution, the processor subsystem accesses memory and makes the change. If the instruction initiates an I/O operation, this subsystem accesses the I/O subsystem required to complete the function and passes control to it.
All instructions are executed in a two-stage pipeline. While one instruction is being executed, the next instruction can be fetched for greater processing efficiency.
Firmware microprogramming provides the interface between software and each subsystem, allowing the system to be tailored for most efficient execution of a given object code set.


All subsystems communicate with each other in a standardized format through the Internal Transfer Subsystem, which employs a common bus for intrasystem data traffic. The internal transfer subsystem controls data traffic, status checking and recording, and automatic answer (complete/incomplete) for the sending subsystem.
The subsystems function concurrent with and independent of each other for maximum processing efficiency.


Input/Output Subsystem components and characteristics are determined by the types of peripherals attached to the system, but can include any or all of the following:

Input/Output Link Controllers - I/O Link Controllers interface with peripherals through I/O Link Adapters, which are either built into individual peripherals or handle strings of peripherals, depending upon the nature of the device. Each I/O Link Controller supports up to four Link Adapters; the number of controllers per system will vary from none to a maximum of four, depending upon individual configuration requirements and 110 options selected.

Common Trunk Controller - Interfaces for standard NCR common trunks can also be included in the system to permit migration of certain existing peripherals that are not adaptable to I/O Link architecture. A maximum of two low- speed (50KB transfer rate) trunks, together with any number of high- speed (1 .2MB) trunks, may be attached to a system so long as the total number of IOLC's and common trunks does not exceed four.

 Integrated Disk Controller - The system will also accommodate one Integrated Disk Controller in addition to the maximum number of I/O Link Controllers and common trunks permitted. The controller drives up to three strings of eight disk spindles and provides direct memory access, so that processing units do not have to be interrupted during data transfer.


The Integrated Memory Subsystem combines main storage with its own interface, timing, and control logic that allows it to function independent of other subsystems. The memory subsystem incorporates single- bit error correction and double-bit error detection. Only double-bit errors are considered hard memory errors.


The optional Integrated Communication Subsystem provides an interface for up to twenty asynchronous or synchronous communication lines operating up to 9600 bps each. Hardware accommodates various line characteristics such as start! stop bits, 7- or 8-bit characters, and control characters. Firmware adjusts for different characteristics on each line allowing simultaneous operation of multiple lines with different options.
The subsystem can be supplemented or replaced by an NCR communications multiplexer
connected to a common trunk.


Configuration options are available to extend the processing range, flexibility, and performance of the NCR V-8450 System.


A complete complement of highly reliable and low-cost peripherals and terminals is available for each system configuration. Peripherals and terminals can be selected on a job requirements basis - or added later as the need arises - as individual models provide features and advantages for specific processing objectives.

lnput/Output Peripherals process punched card, magnetic data cassettes, flexible disks, encoded documents, and print forms and reports.
Magnetic Tape Handlers use 7-or 9-channel, in PE, NRZI, and GCR modes, with recording densities up to 6250 bits per inch and transfer rates up to 1.2 megabytes.
Disk Units include both removable and fixed disks with up to 1092 MB capacity per unit and 1 .2 megabyte transfer rates.
Special and General Purpose Terminals provide point-of-entry service from local or remote locations for all lines of business, and all kinds of applications.


The Core Memory Project. Started 04.02.2005.
Copyright © Aleksandrs Guba. All Rights Reserved